The present invention relates in general to the field of semiconductor design tools, and in particular to a method to optimize performance of an electric circuit design, and a data processing system to optimize performance of an electric circuit design. Still more particularly, the present invention relates to a data processing program and a computer program product for performing a method to optimize performance of an electric circuit design.
A digital integrated circuit is typically built by combining prefabricated elements called “cells”. The cells perform Boolean combinatorial functions or storage. Different cells may perform the same function but use different amounts of power. Typically, the cell with lower power consumption is slower, i.e. takes longer to perform its function. An example for different cells with equal digital function is the usage of different threshold voltage (VT) levels. Here the cells differ just by the thickness of the oxide; all other physical design characteristics are equal. As low power consuming cells are slower it is in many cases impossible to exclusively use these types. Moreover, it is prohibitive to enumerate all candidates since the number of cases to be analyzed grows exponentially with the number of instances of cells.
A simple and known technique arbitrarily picks an instance of a cell, swaps the cell with a lower power consuming one and analyzes the timing impact. If no new timing violations come into existence the swap will be made permanent otherwise it will be revoked.
An enhancement of the technique above is to order the instances by the possible power reduction in a descending way and apply the technique above.
In the Patent Application Publication U.S. 2002/0152409 A1 “METHOD OF POWER CONSUMPTION REDUCTION IN CLOCKED CIRCUITS” by Chu et al. method and apparatus for reducing power consumption of a clocked circuit containing a plurality of latches is disclosed. A first latch, within the plurality of latches, is located which has more than a predetermined slack. The possibility of substituting an available second latch requiring less power to operate is then determined, subject to the constraint that the slack after substitution should still be positive, although it may be less than the predetermined number mentioned above. Where such a possibility is determined to exist, the first latch is then replaced with the available second latch.
In U.S. Pat. No. 7,594,202 B2 “OPTIMIZATION OF CIRCUIT DESIGNS USING A CONTINUOUS SPECTRUM OF LIBRARY CELLS” by de Dood et al. method of optimizing a circuit design having a plurality of library cells is disclosed. In one embodiment, the method includes the steps of providing a plurality of logically equivalent cells that vary in at least one design parameter, the plurality of logically equivalent cells having a relatively continuous spectrum of values of one of the design parameters, evaluating a selected characteristic of the circuit design; and replacing a cell in the circuit design with a cell an equivalent cell.